Referring to FIG. 1, a conventional comparator circuit 10 formed by MOS transistors is shown. In the comparator circuit 10 shown, when an input signal Vin1 is at a higher level than an input signal Vin2, a drain current passing through a transistor Tr3 decreases to reduce the potential at a node N1 (or a gate of a transistor Tr7) substantially to the ground GND level. As a consequence, the transistor Tr7 is turned off, delivering an output signal Vout of an H level at an output terminal To.
On the other hand, when the input signal Vin1 is at a lower level than the input signal Vin2, the drain current passing through the transistor Tr3 increases to raise the potential at the node N1 (or the gate of the transistor Tr7). Consequently, the transistor Tr7 is turned on, passing the drain current of the transistor Tr7 through a resistor R and delivering the output signal Vout of an L level, which is substantially equal to the ground GND level, to the output terminal To.
In this manner, the comparator circuit 10 operates to deliver an output of either H level or L level in accordance with a result of comparison between the both signals Vin1, Vin2.
An op amp circuit is formed by feeding back the output signal Vout as the input signal Vin2. In this instance, the op amp circuit operates to bring the voltage levels of both signals Vin1, Vin2 substantially into coincidence with each other.
More specifically, P-channel MOS transistors Tr1 and Tr2 each have a source connected to a power supply Vcc (high potential bus) and a gate connected to the drain of the transistor Tr1. The gates of both of the transistors Tr1 and Tr2 are connected together. A current source 1 is connected to the drain of the transistor Tr1. The transistors Tr1 and Tr2 form a current mirror circuit. The transistor Tr2 operates as a constant current source, which passes a drain current equal to the current flow through the current source 1.
The drain of the transistor Tr2 is connected to sources of each of the P-channel MOS transistors Tr3 and Tr4. The transistor Tr3 has a drain connected to the drain of an N-channel MOS transistor Tr5. A source of the transistor Tr5 is connected to the ground GND (or low potential bus). A junction between the transistor Tr3 and the transistor Tr5 defines the node N1.
The transistor Tr4 has a drain connected to the drain of an N-channel MOS transistor Tr6 and to the gates of the transistors Tr5 and Tr6. The transistor Tr6 has a source connected to the ground GND. The gates of both of the transistors Tr5 and Tr6 are connected together.
The input signals Vin1, Vin2 are input to the gates of the transistors Tr3 and Tr4, respectively. The transistors Tr3 to Tr6 form a differential input circuit which is activated by the constant current supplied from the transistor Tr2.
An N-channel MOS transistor Tr7 has a gate connected to the node N1, a drain connected to the power supply Vcc through a resistor R, and a source connected to the ground GND. An output terminal To which delivers the output signal Vout is connected to the drain of the transistor Tr7.
Referring now to FIG. 2, a second conventional comparator circuit 20 is shown. In the comparator circuit 20, the resistor R of the comparator circuit 10 is replaced by a P-channel MOS transistor Tr8 having a gate connected to the gates of the transistors Tr1 and Tr2.
The transistor Tr8 operates as a constant current source which supplies an idling current to the output terminal To. The idling current from the transistor Tr8 is chosen to be sufficiently small as compared with a maximum drain current from the transistor Tr7.
In the comparator circuit 20, when the drain current from the transistor Tr7 is greater than the idling current from the transistor Tr8, as attributable to a rise in the potential at the node N1, the output signal Vout is established at its L level.
On the other hand, when the drain current from the transistor Tr7 is less than the idling current from the transistor Tr8, as attributable to a reduction in the potential at the node N1, the output signal Vout is established at its H level.
The comparator circuit 20 may also be operated as an op amp circuit by feeding the output signal Vout back as the input signal Vin2.
Referring to FIG. 3, a third conventional comparator circuit 30 is shown. In the comparator circuit 30 shown, the resistor R of the comparator circuit 10 is replaced by a P-channel MOS transistor Tr9, the gate potential of which is controlled by P-channel MOS transistors Tr10 and Tr11. The transistors Tr7 and Tr9 are chosen such that they exhibit substantially equal load driving capabilities.
The transistor Tr10 has a source connected to the power supply Vcc, a gate connected to the gates of the transistors Tr1 and Tr2 and a drain connected to the gate of the transistor Tr9 and to the source of the transistor Tr11. A constant drain current passes through the transistor Tr10. The transistor Tr11 has a gate connected to the node N1 and a drain connected to the ground GND. A drain current from the transistor Tr10 is chosen to be sufficiently smaller than a maximum drain current of the transistor Tr11.
In the comparator circuit 30, when the transistor Tr7 is turned on as attributable to a rise in the potential at the node N1, the source potential of the transistor Tr11 or the gate potential of the transistor Tr9 rises, causing the transistor Tr9 to be turned off, establishing the output signal Vout at its L level.
On the other hand, when the transistor Tr7 is turned off due to a fall in the potential at the node N1, the source potential of the transistor Tr11 or the gate potential of the transistor Tr9 is reduced, causing the transistor Tr9 to be turned on, establishing the output signal Vout at its H level. In this manner, the transistors Tr7 and Tr9 operate in a push-pull mode in accordance with a change in the potential at the node N1.
The comparator circuit 10 in FIG. 1 (according to the first prior art) has a difficulty obtaining a maximum utilization of the current driving capability of the transistor Tr7. Referring to FIG. 1 again, when the transistor Tr7 is turned off, the source (or discharge) current Iso delivered to a load from the output terminal To is given as follows: EQU Iso=(Vcc-Vout)/R
and the source current varies with a change in the output signal Vout.
The source current Iso is reduced when the resistor R has a relatively high resistance. When a load connected to the output terminal To is excessive, a rise of the output signal Vout from its L to its H level may be retarded.
By contrast, the source current Iso may be increased by reducing the resistance of the resistor R. However, when a sink current Isi is drawn into the transistor Tr7 from the output terminal To as the transistor Tr7 is turned on, the source current Iso may retard the flow of the sink current Isi, thus retarding the falling edge of the output signal Vout. Since the current flow from the power supply Vcc through the resistor R and transistor Tr7 to the ground GND increases, the current dissipation of the comparator circuit 10 increases.
The drain current of an MOS transistor generally increases as the potential difference between the gate potential Vg and the source potential Vs increases. Denoting the gate-source voltage of the transistor Tr3 by Vgs (Tr3) and its source-drain voltage by Vds (Tr3), the potential at the node N1 or the gate potential Vg (Tr7) of the transistor Tr7 is given as follows: EQU Vg(Tr7)=Vin1+Vgs(Tr3)-Vds(Tr3)
When the level of the input signal Vin1 falls, the potential at the node N1 rises. However, the potential at the node N1 cannot rise close to the level of the power supply Vcc as a result of a suppressing effect of the input signal Vin1. This means that it is difficult to achieve a gate potential for the transistor Tr7 which allows its full movement from the supply voltage Vcc to the ground GND level. Similarly, a gate potential for the transistor Tr7 which allows its full movement also cannot be obtained in the second and the third prior circuits 20, 30. Accordingly, the current driving capability of the transistor Tr7 cannot be used to its full extent when the output signal Vout of the L level is delivered, such that the falling rate of the output signal Vout cannot be fully accelerated.
By contrast, in the second circuit 20, it is possible to establish a constant source current Iso which is supplied from the output terminal To to the load by the drain current from the transistor Tr8 when the transistor Tr7 is turned off to deliver the output signal Vout of the H level.
However, when enough source current Iso is secured, the source current Iso retards the flow of the sink current Isi as the transistor Tr7 is turned on to draw the sink current Isi from the output terminal To, such that the falling rate of the output signal Vout is retarded while simultaneously increasing the current dissipation.
In the third circuit 30, a change in the potential at the node N1 is reflected in the gate potential of the transistor Tr9. When the sink current Isi into the transistor Tr7 increases due to a rise in the potential at the node N1, the gate potential of the transistor Tr7 rises, thus limiting the source current Iso. On the other hand, when the sink current Isi into the transistor Tr7 decreases due to a fall in the potential at the node N1, the gate potential of the transistor Tr9 falls to increase the source current Iso. Accordingly, the source current Iso of the transistor Tr9 is controlled in accordance with the load.
The potential difference between the gate of the transistor Tr7 and the gate of the transistor Tr9 corresponds to the gate-source voltage of the transistor Tr11. When the potential at the node N1 is around Vcc/2, the transistors Tr7 and Tr9 are both turned on. Accordingly, an increased current flow from the power supply Vcc through the transistors Tr9 and Tr7 simultaneously to the ground GND, presenting a problem of an increased current dissipation. Since the gate-source voltage of the transistor Tr11 varies due to variations from transistor to transistor during their manufacturing process or a change in the ambient temperatures of the transistors, it is not a simple matter to construct a circuit which accurately maintains the magnitude of the current flow.